Static random access memory (SRAM) devices may be powered by a battery, or other temporary power source, in the event of a power supply failure, in order to retain the data stored therewithin. In prior configurations, a single power supply pin for receiving the power supply voltage from either or both a power supply source or a battery has been provided, so that the user may continue powering the SRAM from an off-chip source. Without special circuitry on-chip, however, the externally applied battery must not only power the array to maintain the stored data therewithin, but must also power the peripheral circuitry such as decoders and sensing circuits. In most SRAM devices, the power dissipation in the array to maintain the stored data is minimal, but the peripheral circuitry may draw significant power from the off-chip battery, decreasing the length of time that the battery is able to maintain the stored data in the array.
On-chip circuitry has been provided which turns off the peripheral circuitry in a battery backup mode, so that the battery applied to the single power supply pin powers only the array and not the peripheral circuitry. One method of such decoupling of the peripheral circuitry from the single power supply pin is to provide a power-down pin, which receives an external signal indicating that the power supply is to be decoupled from the periphery and maintained only for the memory array. When the power-down pin receives a power-down signal, all current sources and DC current paths will be turned off, and all peripheral circuitry will be placed in a high impedance (low leakage) state; this requires a significant amount of gating to accomplish, responsive to the single input signal. A special problem exists for the use of such circuitry responsive to an externally driven power-down pin where the SRAM is fabricated using BiCMOS technology, where both bipolar and MOS transistors are utilized on the same chip, especially where the logic in the peripheral circuitry is realized in emitter-coupled logic (ECL) fashion in the case of a power failure (after which a power-down signal is externally generated and presented to the power-down pin of the SRAM). Internally for the SRAM, V.sub.cc in an ECL SRAM application will generally be referred to as a common ground for maximum ECL signal margin; V.sub.ee will be referred to as a voltage negative with respect to the ground of V.sub.cc. When the circuitry is incorporated in ECL, the power failure causing V.sub.cc to collapse toward V.sub.ee will also cause the ECL buffer receiving the power-down signal to have its differential inputs also collapse toward each other, which may cause the power-down signal presented to the power-down pin to go undetected.
Referring to FIG. 5, another problem exists due to the use of a single power supply pin. FIG. 5 illustrates a cross-sectional diagram of a p-channel MOS transistor as would be incorporated into a CMOS inverter in the BiCMOS SRAM. Source region 100 and drain region 101 are p+ regions diffused into n-type well 102 formed in p-type substrate 104, with gate electrode 105 disposed over gate dielectric 107 between source region 100 and drain region 101. Source region 100 and n-well region 102 is connected nominally to V.sub.cc, the single power supply pin, while the p-type substrate 104 is nominally connected to V.sub.ee. In battery backup mode, it is often preferable for the voltage of the battery to be reduced from the normal operating voltage applied to the single V.sub.cc terminal, for reduction of the power drain on the battery. However, drain region 101 of FIG. 5 may be connected to an external pin which is floating in the battery backup mode. If drain region 101 floats or is otherwise pulled to a voltage above V.sub.cc applied from the battery, the parasitic p-n-p transistor illustrated in FIG. 5 which has drain region 101 as the emitter, n-well region 102 as the base, and substrate 104 as the collector will turn on, draining current from V.sub.cc into n-well 102 to the collector of substrate 104 for bipolar conduction. Such parasitic bipolar conduction would drain a battery connected to the single power supply pin V.sub.cc.
It is therefore an object of this invention to provide a battery backup capability which does not require on-chip power-down circuitry.
It is a further object of this invention to provide such capability which does not excessively drain the battery supply due to bipolar conduction.
Other objects of the invention will become apparent to those of ordinary skill in the art having reference to this specification in conjunction with the drawings.